Post by jlf65 on Mar 28, 2007 16:29:26 GMT -5
ob1 said:
jlf65 said:
What many games do is copy the game code to SDRAM and then use DMA to transfer game data from the ROM as needed.Do you know where are these data transferred to ? SDRAM ? Frame Buffer ?
And do you know which DMA is used ? The 32X, with the settings of the DREQ register, or the SH2, setting SAR1, DAR1 and so on ...?
Well, the Genesis side can always do the normal DMA from the cart; for example, DMA from the cart to vram for updating tiles or maps. DMA from from the cart from the Genesis holds off SH2 access to the cart while in progress. There's plenty of info and examples on that.
DMA on the Mars side involves one or both SH2s. Each SH2 has two DMA channels. They must be run in dual address mode (the programmer specifies both a source and a target). The source can be any of the following: ROM, SDRAM, frame buffer, cache, or the hardware FIFO. The destination can be SDRAM, frame buffer, cache, the hardware FIFO, or the PWM regs.
Note that the hardware FIFO is for passing data from the Genesis to the Mars or vice versa, and is tied to DMA channel0 only. On the Genesis side, the the FIFO can be read/written by DMA or the 68000. Further note that the PWM is tied to DMA channel 1. Because of the tie between the channels, DMA cannot be used to handle the PWM from the Genesis side. You would need to use interrupt driven code - the 68000 would set the PWM on ints (I suppose you COULD use polling, but that's a waste of a lot of good 68000 cpu time). DMA PWM is nearly always from the ROM or SDRAM. You could do something like DMA PWM from the cache or frame buffer, but that is a waste of space in those better used for video.
For example...
DMA from Genesis to frame buffer:
SH2 side:
set SH2 dma0 source to the FIFO (SH2 map address! )
set SH2 dma0 destination to the frame buffer (SH2 map address! )
set SH2 dma0 count to the number of words to transfer
set SH2 dma0 control according to how the data is to be transferred - normally destination incremented, source fixed (always FIFO addy), transfer size = word, module request (request is generated by FIFO), acknowledge mode cleared (generate ack to FIFO), acknowledge level high, detect request by edge, detect rising edge, cycle-steal, dual-address, int disabled (if you wish to know when the DMA is done, set this instead), transfer-end flag cleared, and DMA enable set.
set SH2 dma0 operation to 1 (fixed priority ch0>ch1, add 16 for round robin pri) to start the dma.
All these are in the SH2 manual. The trick is knowing that the hardware FIFO uses a postive edge request for word transfers to DMA channel 0, and takes a positve acknowledge signal.
Genesis side:
CPU transfer - store data to FIFO reg as long as not full until all data transferred
PWM:
The trick with using PWM is knowing the PWM settings are dest fixed (PWM reg), source incremented, module request, ack mode cleared, acknowledge level high, detect request by edge, detect rising edge, cycle-steal, and dual-address. Pretty much the same as the FIFO, but we are going from mem to hw instead of hw to mem.
If you're doing stereo audio, DMA longwords to the left channel (that will set both left and right together). If you are doing one channel or mono, DMA words to the left, right, or mono channel reg specifically.
Memory to Memory (say, ROM to SDRAM or frame buffer):
The settings you want are inc dest, inc source, auto-request, ack mode cleared, acknowledge level high, detect request by edge, detect rising edge, cycle-steal, and dual-address. The transfer size can be word, longword, or 16 bytes, and you can also use the fixed source, or decrement on either source or dest. While fixed dest is possible, it's not very useful on mem to mem transfers. ;D Memory to memory transfers can be done with either DMA channel.