32X FIFO length

[ob1]

I'd like to know the FIFO length.
Gens sources states it is 4 16-bit word long. But using this code :
start68k:
  move.l   #$A15106,a0      ; DREQ Control Register
  move.l   #$A15112,a1      ; FIFO Register
  move.w   #4,(a0)         ; CPU write (68k writes data in FIFO)
  moveq   #0,d1
whileFIFONotFull:
  move.w   (a0),d0
  andi.w   #$80,d0
  bne   FIFOFull
  move.w   d1,(a1)
  addq   #1,d1
  bra   whileFIFONotFull
FIFOFull:
  bra   FIFOFull
end68k:

d1 is 8. So FIFO is 8 16-bit words ?

Does anyone know how big it is ?

[oompa loompa]

i dunno - i never liked using the fifo for communication between the cpu's

[ob1]

What do you prefer so ? CommPort ?
And what about 68k <=> SH2s ?

[jlf65]

Using the FIFOs for inter-CPU communications is an interesting idea. For most things, the COMM registers are sufficient for communications, and what SEGA meant for you to use. The FIFO is meant for being a DMA target/source for copying data between the two sides independent of the CPU communications.

[ob1]

The hardware manual states "(Communication Port) speed is comparatively rapid even if polling by cache-through" and "(SDRAM)This is a wide region able to capture large emounts of data".
So, for short amount of data, use Comm Port, and for bigger loads, use SDRAM.

The figure 3.28 also states that FIFO is 4 word length.

Anyway, I've read a lot of things recently, and it clearly appears to me that FIFO is very well suited for communincation.

[ob1]

The hardware manual supplement cleary states "the configuration of FIFO is 4 words x 2 of block A FIFO and block B FIFO."