32x cart?

[cdoty]

Are 32x cartridge physically different than a normal genesis carts? Does the rom have to be a certain size?

I have two different eprom cartridges, and would like to get them working on the 32x, if possible.

I also have a 16 Mbit Romulator with a Genesis adapter.(http://www.programmersheaven.com/zone8/cat41/13143.htm)

I tried devstertest20.zip on an EPROM board.

Actually I think I know what the problem might be, it looks like I need to byte swap the rom.

[GiGaBiTe]

i thought that SH2's are 32 bit CPU's, so wouldnt it make sense to use 32 bit roms?

[cdoty]

gigabite said:

i thought that SH2's are 32 bit CPU's, so wouldnt it make sense to use 32 bit roms?

Devster says it's a 16 bit rom. I'm guessing the code gets downloaded to the 32x to run.

[jlf65]

gigabite said:

i thought that SH2's are 32 bit CPU's, so wouldnt it make sense to use 32 bit roms?

The SH2's are 32bit and have 32bit access to the SDRAM, but the cart (and ROM) is only 16bit for compatibility reasons. The SH2's have an internal cache, which helps, and you can also copy the code to SDRAM if you want faster access.

What many games do is copy the game code to SDRAM and then use DMA to transfer game data from the ROM as needed.

[GiGaBiTe]

I was reading on the wikipedia that most 32x games were 32 bit cartriges, with some being 16 bit for odd reasons.

[cdoty]

How would that work? Doesn't the genesis only have a 16 bit data bus? Does the 32x have a 32 bit bus?

[GiGaBiTe]

well the SH2 is a 32 bit CPU with a 32 bit bus, so it would make all sense in the world to have 32 bit access to its data.

everything in the genesis is either 16 bit or 8 bit (Z80) but the SH2 controls everything, not the 68000 so it would make sense for the cartridge to be 32 bit.

the only exception would be is if you made both SH2's do the rendering and have the 68000 do the game data, then it would have to be 16 bit for the 68000 to read it.

[jlf65]

The cart on the 32X is still only 16bit. There are no 32bit carts unless they also contain a chip that multiplexes the data to the 16bit bus. The cart port of the 32X is electrically compatible with the plain Genesis, with the carts themselves being a smidge larger than the Genesis carts to prevent you from plugging them into a plain Genesis. People use Genesis cart dumpers to save 32X carts all the time, so there is nothing special about them other than the data contents.

[chaos89dotcom]

jlf65 said:

The cart on the 32X is still only 16bit. There are no 32bit carts unless they also contain a chip that multiplexes the data to the 16bit bus. The cart port of the 32X is electrically compatible with the plain Genesis, with the carts themselves being a smidge larger than the Genesis carts to prevent you from plugging them into a plain Genesis. People use Genesis cart dumpers to save 32X carts all the time, so there is nothing special about them other than the data contents.

I have to agree on this one! I myself opened a genesis cart and a 32X cart and the carts are exactly the same. Except for the rom itself. All connections to the cartridge edge connector from the rom are the same. I used the 32X motocross cart to check this out. And there was only one rom in the 32x cart. The roms are also 42 pin roms. So they must be 16bit roms.

[ob1]

jlf65 said:

What many games do is copy the game code to SDRAM and then use DMA to transfer game data from the ROM as needed.

Do you know where are these data transferred to ? SDRAM ? Frame Buffer ?
And do you know which DMA is used ? The 32X, with the settings of the DREQ register, or the SH2, setting SAR1, DAR1 and so on ...?

[jlf65]

ob1 said:

jlf65 said:

What many games do is copy the game code to SDRAM and then use DMA to transfer game data from the ROM as needed.

Do you know where are these data transferred to ? SDRAM ? Frame Buffer ?
And do you know which DMA is used ? The 32X, with the settings of the DREQ register, or the SH2, setting SAR1, DAR1 and so on ...?

Well, the Genesis side can always do the normal DMA from the cart; for example, DMA from the cart to vram for updating tiles or maps. DMA from from the cart from the Genesis holds off SH2 access to the cart while in progress. There's plenty of info and examples on that.

DMA on the Mars side involves one or both SH2s. Each SH2 has two DMA channels. They must be run in dual address mode (the programmer specifies both a source and a target). The source can be any of the following: ROM, SDRAM, frame buffer, cache, or the hardware FIFO. The destination can be SDRAM, frame buffer, cache, the hardware FIFO, or the PWM regs.

Note that the hardware FIFO is for passing data from the Genesis to the Mars or vice versa, and is tied to DMA channel0 only. On the Genesis side, the the FIFO can be read/written by DMA or the 68000. Further note that the PWM is tied to DMA channel 1. Because of the tie between the channels, DMA cannot be used to handle the PWM from the Genesis side. You would need to use interrupt driven code - the 68000 would set the PWM on ints (I suppose you COULD use polling, but that's a waste of a lot of good 68000 cpu time). DMA PWM is nearly always from the ROM or SDRAM. You could do something like DMA PWM from the cache or frame buffer, but that is a waste of space in those better used for video.

For example...

DMA from Genesis to frame buffer:

SH2 side:
set SH2 dma0 source to the FIFO (SH2 map address! )
set SH2 dma0 destination to the frame buffer (SH2 map address! )
set SH2 dma0 count to the number of words to transfer
set SH2 dma0 control according to how the data is to be transferred - normally destination incremented, source fixed (always FIFO addy), transfer size = word, module request (request is generated by FIFO), acknowledge mode cleared (generate ack to FIFO), acknowledge level high, detect request by edge, detect rising edge, cycle-steal, dual-address, int disabled (if you wish to know when the DMA is done, set this instead), transfer-end flag cleared, and DMA enable set.
set SH2 dma0 operation to 1 (fixed priority ch0>ch1, add 16 for round robin pri) to start the dma.

All these are in the SH2 manual. The trick is knowing that the hardware FIFO uses a postive edge request for word transfers to DMA channel 0, and takes a positve acknowledge signal.

Genesis side:
CPU transfer - store data to FIFO reg as long as not full until all data transferred


PWM:
The trick with using PWM is knowing the PWM settings are dest fixed (PWM reg), source incremented, module request, ack mode cleared, acknowledge level high, detect request by edge, detect rising edge, cycle-steal, and dual-address. Pretty much the same as the FIFO, but we are going from mem to hw instead of hw to mem.

If you're doing stereo audio, DMA longwords to the left channel (that will set both left and right together). If you are doing one channel or mono, DMA words to the left, right, or mono channel reg specifically.

Memory to Memory (say, ROM to SDRAM or frame buffer):
The settings you want are inc dest, inc source, auto-request, ack mode cleared, acknowledge level high, detect request by edge, detect rising edge, cycle-steal, and dual-address. The transfer size can be word, longword, or 16 bytes, and you can also use the fixed source, or decrement on either source or dest. While fixed dest is possible, it's not very useful on mem to mem transfers. ;D Memory to memory transfers can be done with either DMA channel.

[ob1]

jlf65 said:

They must be run in dual address mode (the programmer specifies both a source and a target)
...
Memory to Memory (say, ROM to SDRAM or frame buffer):
The settings you want are inc dest, inc source, auto-request, ack mode cleared, acknowledge level high, detect request by edge, detect rising edge, cycle-steal, and dual-address. The transfer size can be word, longword, or 16 bytes, and you can also use the fixed source, or decrement on either source or dest. While fixed dest is possible, it's not very useful on mem to mem transfers. ;D Memory to memory transfers can be done with either DMA channel.

Great info.
Thank you very much.

[jlf65]

I was thinking about PWM DMA from the Genesis side... while it doesn't look like you can do it directly, it actually is fairly simple to do. First make double buffers in the SDRAM, and have the PWM DMA come from those buffers. Then fill the buffers from the Genesis side. You could use the FIFO to SDRAM DMA for that. The two sets of DMA would be completely independent of each other, one filling the buffers, the other emptying them.

It's a little more overhead then directly PWM DMAing from the Genesis side, but wouldn't tie up the Genesis side as much (FIFO to SDRAM DMA's being very fast, while PWM DMA only occurs at a word/longword every 1/22050th of a sec). As you can see, DMA channel 1 for one of the SH2's would be tied up completely by PWM DMA, so best not to tie up anything else that completely.